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1. general description the 74avc16374-q100 is a 16-bit edge trigge red flip-flop featurin g separate d-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. the 74avc16374-q100 consist of 2 sections of 8 ed ge-triggered flip-flops. a clock input (cp) and an output enable (oe ) are provided per 8-bit section. the 74avc16374-q100 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. to ensure the high-impedance output state during power-up or power-down, noe should be tied to vcc through a pull-up resistor (live insertion). a dynamic controlled output (dco) circuitry is implemented to support termination line drive during transient (see figure 5 and figure 6 ). this product has been qualified to the automotive electronics council (aec) standard q100 (grade 3) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 3) ? specified from ? 40 ? c to +85 ? c ? wide supply voltage range from 1.2 v to 3.6 v ? complies with jedec standards: ? jesd8-7 (1.2 v to 1.95 v) ? jesd8-5 (1.8 v to 2.7 v) ? jesd8-1a (2.7 v to 3.6 v) ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? cmos low power consumption ? input/output tolerant up to 3.6 v ? dynamic controlled output (dco) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation ? low inductance multiple v cc and gnd pins to minimize noise and ground bounce ? supports live insertion 74avc16374-q100 16-bit edge triggered d-type f lip-flop; 3.6 v tolerant; 3-state rev. 1 ? 16 september 2013 product data sheet
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 2 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74AVC16374DGG-Q100 ? 40 ? c to +85 ? c tssop48 plastic thin shri nk small outline package; 48 leads; body width 6.1 mm sot362-1 fig 1. iec logic symbol fig 2. logic symbol 23 mna577 37 12 11 9 8 6 5 47 46 44 43 41 40 38 1d7 1d0 1d1 1d2 1d3 1d4 1d5 1d6 2 3 1q7 1q6 1q5 1q4 1q3 1q2 1q0 1q1 26 22 20 19 17 16 36 35 33 32 30 29 27 2d5 2d0 2d1 2d2 2d3 2d4 13 14 2q5 2q4 2q3 2q2 2q1 2q0 24 25 2en 1oe 1 1en 1cp 2oe 2cp 48 c1 c2 1d 1 2d 2 2d7 2d6 2q7 2q6 mna576 1q0 1q1 1cp 2cp 1q2 1q3 1q4 1q5 1q6 1q7 1oe 47 46 48 25 44 43 41 40 38 37 2 3 1 5 6 8 9 11 12 24 2q0 2q1 2q2 2q3 2q4 2q5 2q6 2q7 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 2d0 2d1 2d2 2d3 2d4 2d5 2d6 2d7 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 2oe
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 3 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state fig 3. logic diagram mna578 1cp d cp q 1oe to 7 other channels ff1 1q0 1d0 2cp d cp q 2oe to 7 other channels ff9 2q0 2d0
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 4 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 5. pinning information 5.1 pinning 5.2 pin description fig 4. pin configuration $9&4 2( &3 4 ' 4 ' *1' *1' 4 ' 4 ' 9 && 9 && 4 ' 4 ' *1' *1' 4 ' 4 ' 4 ' 4 ' *1' *1' 4 ' 4 ' 9 && 9 && 4 ' 4 ' *1' *1' 4 ' 4 ' 2( &3 ddd table 2. pin description symbol pin description 1oe 1 output enable input (active low) 1q0 to 1q7 2, 3, 5, 6, 8, 9, 11, 12 3-state flip-flop outputs gnd 4, 10, 15, 21, 28, 34, 39, 45 ground (0 v) v cc 7, 18, 31, 42 supply voltage 2q0 to 2q7 13, 14, 16, 17, 19, 20, 22, 23 3-state flip-flop outputs 2oe 24 output enable input (active low) 2cp 25 clock input 2d0 to 2d7 36, 35, 33, 32, 30 , 29, 27, 26 data input/output 1d0 to 1d7 47, 46, 44, 43, 41 , 40, 38, 37 data input/output 1cp 48 clock input
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 5 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 6. functional description [1] h = high voltage level h = high voltage level one set-up time prior to the low-to-high cp transition l = low voltage level l = low voltage level one set-up time prio r to the low-to-high cp transition z = high-impedance off-state ? = low-to-high cp transition 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] above 60 ? c, the value of p tot derates linearly with 5.5 mw/k. table 3. function table [1] operating modes inputs internal flip-flops outputs noe ncp ndn nqn load and read register l ? il l l ? hh h load register and disable outputs h ? il z h ? hh z table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +4.6 v i ik input clamping current v i < 0 v ?? 50 ma v i input voltage [1] ? 0.5 +4.6 v i ok output clamping current v o < 0 v ? 50 - ma v o output voltage output high or low [1] ? 0.5 v cc + 0.5 v output 3-state [1] ? 0.5 +4.6 v i o output current v o =0v tov cc - ? 50 ma i cc supply current - +100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +85 ? c [2] -500 mw
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 6 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 8. recommended operating conditions 9. static characteristics table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage according to jedec low voltage standards 1.4 - 1.6 v 1.65 - 1.95 v 2.3 - 2.7 v 3.0 - 3.6 v for low-voltage applications 1.2 - 3.6 v v i input voltage 0 - 3.6 v v o output voltage output high or low 0 - v cc v output 3-state 0 - 3.6 v t amb ambient temperature in free air ? 40 - +85 ?c ? t/ ? v input transition rise and fall rate v cc = 1.4 v to 1.6 v 0 - 40 ns/v v cc = 1.65 v to 2.3 v 0 - 30 ns/v v cc = 2.3 v to 3.0 v 0 - 20 ns/v v cc = 3.0 v to 3.6 v 0 - 10 ns/v table 6. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit t amb = ? 40 ? c to +85 ?c v ih high-level input voltage v cc = 1.2 v v cc --v v cc = 1.4 v to 1.6 v 0.65 ? v cc 0.9 - v v cc = 1.65 v to 1.95 v 0.65 ? v cc 0.9 - v v cc = 2.3 v to 2.7 v 1.7 1.2 - v v cc = 3.0 v to 3.6 v 2.0 1.5 - v v il low-level input voltage v cc = 1.2 v - - gnd v v cc = 1.4 v to 1.6 v - 0.9 0.35 ? v cc v v cc = 1.65 v to 1.95 v - 0.9 0.35 ? v cc v v cc = 2.3 v to 2.7 v - 1.2 0.7 v v cc = 3.0 v to 3.6 v - 1.5 0.8 v v oh high-level output voltage v i = v ih or v il i o = ? 100 ? a; v cc = 1.65 v to 3.6 v v cc ? 0.20 v cc -v i o = ? 3 ma; v cc = 1.4 v v cc ? 0.35 v cc ? 0.23 - v i o = ? 4ma; v cc = 1.65 v v cc ? 0.45 v cc ? 0.25 - v i o = ? 8ma; v cc = 2.3 v v cc ? 0.55 v cc ? 0.38 - v i o = ? 12 ma; v cc = 3.0 v v cc ? 0.70 v cc ? 0.48 - v
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 7 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state [1] all typical values are measured at t amb =25 ? c. 9.1 graphs v ol low-level output voltage v i = v ih or v il i o =100 ? a; v cc = 1.65 v to 3.6 v - gnd 0.20 v i o =3 ma; v cc = 1.4 v - 0.10 0.35 v i o =4ma; v cc = 1.65 v - 0.10 0.45 v i o =8ma; v cc = 2.3 v - 0.26 0.55 v i o =12ma; v cc = 3.0 v - 0.36 0.70 v i i input leakage current per pin; v i =v cc or gnd; v cc = 1.4 v to 3.6 v -0.12.5 ? a i off power-off leakage current v i or v o =3.6v; v cc = 0.0 v - ? 0.1 ? 10 ? a i oz off-state output current v i =v ih or v il ; v o =v cc or gnd v cc = 1.4 v to 2.7 v - 0.1 5 ? a v cc = 3.0 v to 3.6 v - 0.1 10 ? a i cc supply current v i =v cc or gnd; i o = 0 a v cc = 1.4 v to 2.7 v - 0.1 20 ? a v cc = 3.0 v to 3.6 v - 0.2 40 ? a c i input capacitance - 5 - pf table 6. static characteristics ?continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit fig 5. output voltage as a function of the high-level output current. fig 6. output voltage as a function of the low-level output current. v oh (v) 04 3 12 mna506 -200 -100 0 i oh (ma) -300 1.8 v 2.5 v 3.3 v v ol (v) 04 3 12 mna507 100 200 300 i ol (ma) 0 1.8 v 2.5 v 3.3 v
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 8 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 10. dynamic characteristics table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v). t r = t f ? 2 ns. for test circuit, see figure 10 . symbol parameter conditions ? 40 ? c to +85 ?c unit min typ [2] max t pd propagation delay ncp to nqn; see figure 7 [1] v cc = 1.2 v - 3.1 - ns v cc = 1.4 v to 1.6 v 1.2 2.4 8.4 ns v cc = 1.65 v to 1.95 v 1.0 2.0 6.7 ns v cc = 2.3 v to 2.7 v 0.8 1.5 4.1 ns v cc = 3.0 v to 3.6 v 0.7 1.3 3.3 ns t en enable time noe to nqn, nbn; see figure 8 [1] v cc = 1.2 v - 5.4 - ns v cc = 1.4 v to 1.6 v 1.6 3.9 8.5 ns v cc = 1.65 v to 1.95 v 2.3 3.3 6.7 ns v cc = 2.3 v to 2.7 v 0.9 2.3 4.3 ns v cc = 3.0 v to 3.6 v 0.7 2.0 3.4 ns t dis disable time noe to nqn; see figure 8 [1] v cc = 1.2 v - 5.6 - ns v cc = 1.4 v to 1.6 v 2.5 4.5 9.4 ns v cc = 1.65 v to 1.95 v 1.8 3.3 7.8 ns v cc = 2.3 v to 2.7 v 1.0 1.8 4.2 ns v cc = 3.0 v to 3.6 v 1.2 2.0 3.9 ns t w pulse width high; ncp; see figure 7 v cc = 1.2 v - 0.8 - ns v cc = 1.4 v to 1.6 v - 0.5 - ns v cc = 1.65 v to 1.95 v 3.1 0.3 - ns v cc = 2.3 v to 2.7 v 2.5 0.2 - ns v cc = 3.0 v to 3.6 v 2.5 0.2 - ns t su set-up time ndn to ncp; see figure 8 v cc =1.2v - ? 0.6 - ns v cc = 1.4 v to 1.6 v 2.7 ? 0.3 - ns v cc = 1.65 v to 1.95 v 1.9 ? 0.3 - ns v cc = 2.3 v to 2.7 v 1.4 ? 0.2 - ns v cc = 3.0 v to 3.6 v 1.4 ? 0.1 - ns t h hold time ndn to ncp; see figure 8 v cc = 1.2 v - 0.8 - ns v cc = 1.4 v to 1.6 v 1.3 0.7 - ns v cc = 1.65 v to 1.95 v 1.2 0.6 - ns v cc = 2.3 v to 2.7 v 1.1 0.5 - ns v cc = 3.0 v to 3.6 v 1.1 0.4 - ns
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 9 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state [1] t pd is the same as t plh and t phl . t en is the same as t pzl and t pzh . t dis is the same as t plz and t phz . [2] typical values are measured at t amb =25 ? c and v cc = 1.2 v, 1.5 v, 1.8 v, 2.5 v and 3.3 v respectively. [3] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in volts n = number of inputs switching ? (c l ? v cc 2 ? f o ) = sum of the outputs. 11. waveforms f max maximum frequency see figure 8 v cc =1.2v - 250 - mhz v cc = 1.4 v to 1.6 v - 300 - mhz v cc = 1.65 v to 1.95 v 160 320 - mhz v cc = 2.3 v to 2.7 v 200 350 - mhz v cc = 3.0 v to 3.6 v 200 350 - mhz c pd power dissipation capacitance per input; v i =gndtov cc [3] outputs enabled - 66 - pf outputs disabled - 1 - pf table 7. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v). t r = t f ? 2 ns. for test circuit, see figure 10 . symbol parameter conditions ? 40 ? c to +85 ?c unit min typ [2] max measurement points are given in table 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 7. clock input (ncp) to out put (nqn) propagation delays mna579 ncp input nqn output t phl t plh t w v m v oh v i gnd v ol v m v m 1/f max
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 10 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state measurement points are given in table 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 8. 3-state enable and disable times mna478 t plz t phz outputs disabled outputs enabled v y v x outputs enabled output low-to-off off-to-low output high-to-off off-to-high noe input v i v ol v oh v cc v m gnd gnd t pzl t pzh v m v m measurement points are given in table 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 9. data set-up and hold times for ndn input to ncp input mna580 gnd gnd t h t su t h t su v m v m v m v i v oh v ol v i nqn output ncp input ndn input
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 11 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state table 8. measurement points supply voltage v m input v cc v i t r =t f v x v y 1.2 v 0.5 ? v cc v cc ? 2ns v ol + 0.15 v v oh ? 0.15 v 1.4 v to 1.6 v 0.5 ? v cc v cc ? 2ns v ol + 0.15 v v oh ? 0.15 v 1.65 v to 1.95 v 0.5 ? v cc v cc ? 2ns v ol + 0.15 v v oh ? 0.15 v 2.3 v to 2.7 v 0.5 ? v cc v cc ? 2ns v ol + 0.15 v v oh ? 0.15 v 3.0 v to 3.6 v 0.5 ? v cc v cc ? 2ns v ol + 0.3 v v oh ? 0.3 v test data is given in table 9 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 10. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae331 v ext v cc v i v o dut c l r t r l r l g table 9. test data supply voltage input load v ext v i t r , t f c l r l t plh , t phl t plz , t pzl t phz , t pzh 1.2 v v cc ? 2 ns 15 pf 2 k ? open 2 ? v cc gnd 1.4 v to 1.6 v v cc ? 2 ns 15 pf 2 k ? open 2 ? v cc gnd 1.65 v to 1.95 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 2.3 v to 2.7 v v cc ? 2ns 30pf 500 ? open 2 ? v cc gnd 3.0 v to 3.6 v v cc ? 2ns 30pf 500 ? open 2 ? v cc gnd
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 12 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 12. package outline fig 11. package outline sot362-1 (tssop48) references outline version european projection issue date iec jedec jeita sot362-1 mo-153 sot362-1_po 03-02-19 13-08-05 unit mm max nom min 0.15 0.28 0.2 12.6 0.5 0.8 a dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 a 1 a 2 1.05 a 3 b p cd (1) 8 e (2) eh e l 1 l p qvw 1.2 0.25 0.1 0.25 0.08 yz 7.9 0.4 6.0 0.35 0.05 0.17 0.1 12.4 0.4 0 0.85 8.3 0.8 6.2 0.50 pin 1 index va a d l p q e z c l 12 4 48 25 e w y x a h e b p a 1 a 2 detail x (a 3 ) 0 5 mm scale 2.5
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 13 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test mil military ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice order number supersedes 74avc16374_q100 v.1 20130916 product data sheet - - -
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 14 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74avc16374_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 16 september 2013 15 of 16 nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74avc16374-q100 16-bit edge triggered d-type flip-flop; 3.6 v tolerant; 3-state ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 september 2013 document identifier: 74avc16374_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 9.1 graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 14 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 contact information. . . . . . . . . . . . . . . . . . . . . 15 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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